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CDB4923 CDB49300 Evaluation Board for CS4923/CS49300 Families
Features
l CDB4923
Description
The CDB4923 and CDB49300 customer development boards provide the means to fully evaluate the CS4923/4/5/6/7/8 and CS49300 family of audio decoders. Compressed data can be delivered in IEC61937 format via the S/PDIF port and in bursty mode via the PC interface. PCM data can be accepted through the digital input connectors or from the on-board ADC. Six channels of audio are provided on the six analog outputs and on three optical S/PDIF transmitters. CLKIN for the DSP can be derived either from the on-board oscillator or the external PLL. MCLK can be extracted from incoming S/PDIF streams, generated with the external PLL, or mastered by the audio decoder. The CDB4923/300 incorporates a Crystal Multichannel Audio Decoder, the CS4340 24-Bit Audio D/A Converter, the CS8414 Digital Audio Interface Receiver, the CS8404A Digital Audio Interface Transmitter, and the CS5334 20-Bit Stereo A/D Converter. ORDERING INFORMATION CDB4923 CDB49300 Evaluation Board Evaluation Board
demonstrates 5.1 channel decode capability of the CS4923 family l CDB49300 demonstrates 5.1 channel decode capability of CS49300 family l 6 discrete analog outputs driven by CS4340 DACs l 4 S/PDIF optical outputs l Accepts analog input, S/PDIF digital input, Bursty compressed data l Discrete PLL which can provide multiple sampling frequencies l Interfaces to a personal computer through the parallel port l Stake headers provide convenient location for direct wiring to control signals from offboard microcontroller l Interface for external memory card l Digital and analog patch areas
I
Digital Input
Digital Output
CS8404A
CS8404A
CS8404A
CS4340
+2.5V
CS8414
+3.3V
CS4340
Analog Output
RESET
CS4340
CS492x CS493xx
Control Interface
DIGITAL SOUND
TM
PLD
Stereo Analog In
CS5334 PLL OSC
CRYSTAL
(R)
PROC ESSIN G
Patch Area
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
JAN `00 DS262DB2 1
CDB4923 CDB49300
TABLE OF CONTENTS
1. CDB4923 VS. CDB49300 ......................................................................................................... 5 1.1 DSP Power ........................................................................................................................ 5 1.2 DSP PLL Filter ................................................................................................................... 5 2. OPERATION ............................................................................................................................. 5 2.1 Power Requirements ......................................................................................................... 6 2.2 Dolby Considerations ........................................................................................................ 7 3. DIGITAL SIGNAL PROCESSOR ............................................................................................. 7 3.1 Control Signals ................................................................................................................... 7 3.2 External Memory ................................................................................................................ 8 4. CONTROL ................................................................................................................................. 8 5. DATA SELECTION ................................................................................................................... 9 5.1 Provided Mode ................................................................................................................. 10 5.1.1 Control ................................................................................................................. 10 5.1.2 Data ..................................................................................................................... 10 5.1.3 Audio Clocking .................................................................................................... 12 5.2 External Mode .................................................................................................................. 12 6. CLOCKING ............................................................................................................................. 14 6.1 DSP Clock ........................................................................................................................ 14 6.2 MCLK ............................................................................................................................... 15 6.3 LRCLK and SCLK ............................................................................................................ 15 7. INPUT ...................................................................................................................................... 16 7.1 Analog Input ..................................................................................................................... 16 7.2 Digital Input ...................................................................................................................... 16 8. OUTPUT .................................................................................................................................. 17 8.1 Analog Output .................................................................................................................. 17 8.2 Analog Output Protection Circuitry ................................................................................... 17 8.3 Digital Output ................................................................................................................... 17 9. APPENDIX A: SCHEMATICS ...................................................................................... 18 ..................................................... 37 10. APPENDIX D: BILL OF MATERIALS .................................................................................. 34 11. APPENDIX E: EXTERNAL MEMORY SCHEMATICS
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Dolby is a registered trademark of Dolby Laboratories Licensing Corporation DTS is a registered trademark of DTS, Inc. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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12. APPENDIX F: BOARD CONTROL SOFTWARE ................................................................. 39 13. APPENDIX G: IC COMPONENT LISTING BY FUNCTION ................................................. 42 13.1 Power ............................................................................................................................. 42 13.2 Reset .............................................................................................................................. 42 13.3 Clocking.......................................................................................................................... 42 13.4 Signal Routing/Level Conversion ................................................................................... 42 13.5 DSP ................................................................................................................................ 42 13.6 Input................................................................................................................................ 42 13.7 Output............................................................................................................................. 42 14. APPENDIX H: JUMPERS LISTED BY FUNCTION ............................................................. 43 14.1 Audio Input Jumpers....................................................................................................... 43 14.2 Audio Output Jumpers .................................................................................................... 43 14.3 DSP Jumpers ................................................................................................................. 43 14.4 Power Jumpers............................................................................................................... 44 14.5 System Clocking Jumpers .............................................................................................. 44 15. APPENDIX I: JUMPERS LISTED BY NUMBER .................................................................. 46 16. APPENDIX J: SWITCH SUMMARY ..................................................................................... 47
LIST OF FIGURES
Figure 1. External Memory Example............................................................................................... 9 Figure 2. CDB4923/300 Data Paths.............................................................................................. 11 Figure 3. Audio Clocking ............................................................................................................... 12 Figure 4. Audio Clocking ............................................................................................................... 12 Figure 4. CS492x/CS493xx........................................................................................................... 18 Figure 5. System Power................................................................................................................ 19 Figure 6. PC Interface ................................................................................................................... 20 Figure 7. Control Logic.................................................................................................................. 21 Figure 8. Clocking ......................................................................................................................... 22 Figure 9. Analog Input................................................................................................................... 23 Figure 10. Digital Input .................................................................................................................. 24 Figure 11. D/A Converters ............................................................................................................ 25 Figure 12. Analog Output .............................................................................................................. 26 Figure 13. Digital Output ............................................................................................................... 27 Figure 14. Top Layer..................................................................................................................... 28 Figure 15. Bottom Layer................................................................................................................ 29 Figure 16. SSTOP......................................................................................................................... 30 Figure 17. ASYSTOP .................................................................................................................... 31 Figure 18. Layer 2 ......................................................................................................................... 32 Figure 19. Layer 3 ......................................................................................................................... 33 Figure 20. CRD4923-MEM Schematic.......................................................................................... 37 Figure 21. CDB49300-MEM Schematic ........................................................................................ 38
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CDB4923 CDB49300
LIST OF TABLES
Table 1. CS492x/CS493xx Host Interface Mode Selection............................................................. 8 Table 2. Data Selection Modes (PLD version AB-X)..................................................................... 10 Table 3. PROVIDED Data Selection Modes (PLD version AB-X) ................................................. 11 Table 4. Digital Audio Sources ...................................................................................................... 11 Table 5. Clocking Descriptions...................................................................................................... 12 Table 6. DSP Pins Tri-Stated by U11 in PLD Mode 0 ................................................................... 13 Table 7. DSP Pins Tri-Stated by U11 in PLD Mode 1 ................................................................... 13 Table 8. Clocking Descriptions...................................................................................................... 13 Table 9. Data Selection Modes (Switch S3, PLD Version AB-X) .................................................. 14 Table 10. EXTERNAL Data Selection Modes (PLD Version AB-X) .............................................. 14 Table 11. Board Clocking Configurations (J37)............................................................................. 14 Table 12. PCLK Configurations..................................................................................................... 15 Table 13. Audio Frequency Selection (J58) .................................................................................. 15 Table 14. CS5334 Digital Output Formats (S4)............................................................................. 16 Table 15. Digital Output Format settings for CS8414 (S1)............................................................ 16 Table 16. CS4340 Digital Input Formats (S4) ............................................................................... 17 Table 17. Digital Input Format settings for CS8404A (S2) ............................................................ 17 Table 18. CS492x/CS493xx Host Interface Mode Selection......................................................... 47 Table 19. CS5334 Digital Output Formats (S4)............................................................................. 47 Table 20. CS4340 Digital Input Formats (S4) ............................................................................... 47 Table 21. Digital Output Format settings for CS8414 (S1)............................................................ 47 Table 22. PCLK Configurations..................................................................................................... 48 Table 23. Digital Input Format settings for CS8404A (S2) ............................................................ 48 Table 24. Data Selection Modes (Switch S3, PLD Version AB-X) ................................................ 48
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1. CDB4923 VS. CDB49300
The CDB4923 and CDB49300 are two customer development boards built from a single platform the CDB4923/300. This development board replaces the CDB4923 Rev. A and Rev. B. Although the CDB4923/CDB49300 boards look very similar, it is important to be aware that when shipped from the factory, the CDB4923 is configured for only the CS4923 family of audio decoders and the CDB49300 is configured only for the CS49300 family of audio decoders. The features distinguishing the two boards are the following: * * DSP Power Setting DSP PLL Filter Topology * C155 = 0.22 F
The relevant PLL filter components for the CDB49300 are: * * * R246 = 33 k C155 = 0.22 F C113 = 0.01 F
Although the boards are tailored for one specific family of audio decoders, the operation of the CDB4923 and CDB49300 is effectively the same. This document will generically refer to the CDB4923/300 except in those instances where there is a difference between the boards.
2. OPERATION
The CDB4923/300 is designed to allow full evaluation of the CS4923 family and CS49300 family of audio DSPs. The members of each audio decoder family are electrically equivalent, so it is possible to use any member of the CS4923 family in the CDB4923 and any member of the CS49300 family in the CDB49300. In the context of this document, CS492x should be interpreted as any member of the CS4923 family and CS493xx should be understood to be any member of the CS49300 family. The CDB4923/300 is composed of 8 distinct regions: DSP, Control Interface, Control Logic, Clocks, Analog I/O, Digital I/O, Patch area, and Power. Each board region has a number of components and will be briefly discussed below. A more thorough description of each will be given in dedicated sections of this document which can be quickly located in the Table of Contents. The DSP section includes the audio decoder (CS492x Multichannel Audio Decoder or CS493xx Universal Audio Decoder) under evaluation, jumpers for controlling DSP power and DSP configuration pins, and stake headers which provide access to all relevant DSP pins. The jumpers allow the user to select between +2.5 V or +3.3 V on the DSP power pins (pre-configured at the factory for the
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1.1
DSP Power
The CS4923 family is designed to operate with a core voltage of +3.3 V, and the CDB4923 is shipped with the DSP Power jumper in the +3.3 V position. The CS49300 family is designed to operate with a core voltage of +2.5 V, and the CDB49300 is shipped with the DSP Power jumper in the +2.5 V position. Attempting to use an audio decoder on the wrong board (e.g., CS49300 on a CDB4923) can cause unpredictable results and damage the decoder.
1.2
DSP PLL Filter
The PLL of the CS4923 is different than that of the CS49300. Consequently, the optimized external PLL filters for each family of audio decoders is different. The CDB4923 is optimized for the CS4923 family and the CDB49300 is optimized for the CS49300 family. Attempting to use an audio decoder on the wrong board (e.g., CS49300 on a CDB4923) can cause unpredictable results. Specifically, the relevant PLL filter components for the CDB4923 are: * R246 = 0
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CDB4923 CDB49300
proper voltage), configure the audio decoder for different host communication modes and select the clock source for the DSP (internal PLL or external clock). The stake headers provide a convenient location for probing signal values and also serve as the interface to the CRD4923-MEM (for use with CS492x only) or CDB49300-MEM (for use with the CS493xx only) external memory expander cards. The control interface of the CDB4923/300 is composed of a 25 pin connector designed to accept a parallel port cable, a programmable logic device (PLD), and two TTL buffers designed to buffer the sixteen signal lines coming from the PC. Using the software provided with the demonstration board, the user can download code to the DSP, configure the application code running on the DSP, perform a reset of the DSP, and deliver compressed audio files to the DSP. An additional control interface is provided on the J11 and J12 stake headers when the PLD is placed into an external interface mode as described in Data Selection. The majority of the control logic for this board is found in the PLD. The PLD latches all signals coming from the parallel port interface, performs all I/O routing on the board, and provides level conversion from +5 V to +3.3 V/+2.5 V depending on the setting of the I/O power jumper (J63) for the PLD. A dip switch is used to control different data/clock routing configurations. There is also an external reset chip (MAX708) which is responsible for system reset at power-up and when the digital power begins to fail. The sources for the main DSP clock on the CDB4923/300 are the oscillator and the external PLL. When the oscillator is chosen, the main DSP clock frequency can be either the 27 MHz or 12.288 MHz oscillator provided with the board. When properly configured the external PLL can provide a processor clock frequency ranging from 33 MHz to 81 MHz. When the external PLL is used for the DSP processor clock, it can also be used to master the system oversampling clock, MCLK. The CDB4923/300 features six channels of analog output provided by three CS4340 DACs. The outputs are provide a 3.5 Vpp signal, and each output has protection circuitry to protect against speaker 'popping'. A DIP switch is provided for changing the data format accepted by the CS4340. There is a stereo analog input on the CDB4923/300 which is designed to interface to line levels of up to 2 Vrms. The analog to digital conversion is performed by the CS5334. A DIP switch is provided for changing the format of the audio data provided by the CS5334. Input and output ports are provided for S/PDIF digital audio streams (IEC60958 and IEC61937). An incoming S/PDIF stream can be supplied either with an optical cable or coaxial cable. The S/PDIF outputs of the CDB4923/300 are all optical. The information from the AUDATA0-2 pins of the CS492x are transmitted on AOUT_DIG0-2 using digital audio interface transmitters (CS8404A). Optical output J43 is connected directly to the S/PDIF transmitter of the DSP. DIP switches are provided for changing the serial audio format of the data provided by the CS8414 and the data accepted by the CS8404A. The CDB4923/300 provides both analog and digital patch areas. The digital patch area provides access to both +5 V and DSP Power (voltage of the CS492x/CS493xx core). These patch areas are very useful when prototyping circuit modifications. They can also be used as a place to connect signal buffers when using the CDB4923/300 in an external interface mode.
2.1
Power Requirements
This board is composed of about 75% digital logic which is fed by the +5 V power supply. Since the CS492x is a +3.3 V part and the CS493xx is a +2.5 V part, there are also +3.3 V and +2.5 V voltDS262DB2
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CDB4923 CDB49300
age regulators on the board (U8 and U27) which are used to power the DSP and the I/O pads of the PLD (U11). The +12 V and -12 V supplies are used to power the input buffers on the analog side of the board. The power section of the CDB4923/300 can be found in Figure 5. The CDB4923/300 requires a +5 V input on J23 and a digital ground connected to J24 in order to power the digital section of the board. The analog portion requires a +12 V supply on binding post J21, -12 V on J57, and analog ground connected to J22. This document and all other documentation pertaining to the CS493xx family of decoders can be found at the following website:
http://www.cirrus.com/products/overviews/cs49300.html
2.2
Dolby Considerations
It should be noted by the system designer that additional circuitry may be required in order to obtain Dolby Certification (e.g., analog bass management). System requirements are dependent upon the nature of the end product and which group of Dolby Certification is required. The designer should consult the Dolby Licensee Information Manual and contact Dolby Laboratories to determine exactly what is required to meet Dolby specifications for a particular system.
As the focus of the board, the CS492x/CS493xx performs all processing of digital audio. The DSP section of the board is illustrated in Figure 4. The CS492x/CS493xx can be fed compressed data or linear PCM from various sources. However, it should be noted that each load of application software for the DSP is designed to process a specific data type, e.g. DTS application code does not process linear PCM. Please reference the appropriate software application note (i.e. AN120-AN123, AN140 or AN161-AN163) to determine which hardware configurations and audio data types are supported.
3.1
Control Signals
3. DIGITAL SIGNAL PROCESSOR
The CS492x/CS493xx (U1) must be downloaded with application code and configured for operation each time that it is powered up. Each time the decoder needs to be reconfigured, the host must send hardware configuration and application configuration messages to the DSP. A complete description of the software applications and their messaging protocol can be found in application notes AN120AN123, AN140 for the CS492x and AN161AN163 for the CS493xx. Please note that this document and all other documentation pertaining to the CS492x family of decoders can be found at the following website:
http://www.cirrus.com/products/overviews/cs4923.html
The host interface to the DSP, which allows code download and other communication, can be accessed through the parallel port interface (J29) or by placing the control PLD into an external interface mode. In the external interface mode the user can drive the signal pins of the DSP by tapping into the signals present on headers J11 and J12. More information on selecting the host control mode can be found in Data Selection. The host interface mode of the DSP is selected at the rising edge of reset and is programmable. The communication mode is determined by the states of the RD, WR, and PSEL pins when the DSP comes out of reset, as described in the CS4923/4/5/6/7/8/9 datasheet and the CS49300 datasheet. Each mode is described in the CS4923/4/5/6/7/8/9 Hardware User's Guide (AN115) and the CS49300 datasheet. There are six jumpers used to directly control the CS492x/CS493xx. Jumpers J2 (WR), J3 (RD), and J62 (PSEL) are used to select the host interface mode for the CS492x/CS493xx. Table 1 lists the jumper settings required for all four host interface modes. Note that the CDB4923/300 requires
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CDB4923 CDB49300
PSEL==1 when configuring for I2C mode because PSEL and SCDIO are multiplexed onto the same pin. Two of the DSP jumpers are designed to act as current measurement points for the CS492x/CS493xx. Jumper J59 is the analog current measurement point, and it must be installed for the PLL to function. Jumper J60 is the digital current measurement point, and it must be installed in order to supply power to the digital logic of the CS492x/CS493xx. Jumper J1 is the clock selection jumper. When J1 is in the 'CLKIN' position, the clock present on pin 30 of the DSP (CLKIN) will drive the internal DSP clocks directly. When J1 is in the 'PLL' position, the clock present at pin 30 is used as the reference clock for the CS492x/CS493xx internal PLL. The frequency required for the reference clock when using the internal PLL is application code dependent, so the relevant application code user's guide should be consulted to determine which frequency to provide.
RD J3 0 1 1 1 WR J2 1 0 1 1 PSEL J62 1 X 0 1 Host Interface Mode Serial I2C (PSEL==SCDIO) Serial SPI 8-bit Intel 8-bit Motorola
CRD4923-MEM external memory board is tailored for the CDB4923. The schematic for CRD4923MEM can be found in Figure 20. The CS493xx family has integrated DTS tables, so a ROM is required only for autoboot. The CS493xx also has a static RAM interface. The CDB49300-MEM external memory board is tailored for the CDB49300. The CDB49300-MEM schematic can be found in Figure 21. The CDB4923/300 has been designed to interface to both the CRD4923-MEM and CDB49300-MEM daughter boards. The card plugs directly on to J11 oriented such that the CS492x/CS493xx is not covered, as shown in Figure 1. Please consult the memory map associated with the revision of ROM installed in the memory card to determine which code loads are available. The memory map can be found in the `.fmt' file found on the included floppy.
4. CONTROL
Control of the CS492x/CS493xx can be accomplished in two ways. The CDB4923/300 is shipped with a parallel computer cable which can be attached to the parallel port (LPT1, LPT2, or LPT3) of any computer which has a Windows or DOS based operating system. The parallel port (J29) interface circuitry is illustrated in Figure 6. The software shipped with the CDB4923/300 is based on command-line programs which must be executed from a DOS prompt. The CDB4923/300 software provides the means to reset the CS492x/CS493xx, write control data to the DSP, read control data from the DSP, and deliver compressed audio. A detailed description of the software can be found in Appendix F: Board Control Software. Alternatively, the board can be put into a mode which tri-states all connections between the PLD and the DSP (full external mode), or a mode that tri-states the control lines (external control mode) of the CS492x/CS493xx while still driving the data
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Table 1. CS492x/CS493xx Host Interface Mode Selection
3.2
External Memory
Some CDB4923/300 boards may be shipped with an external memory board. There two different external memory boards available: * * CRD4923-MEM - external ROM for CS492x CDB49300-MEM - external ROM and RAM for CS493xx
The CS492x requires an external ROM for autoboot, and the CS4926 requires an external ROM when processing DTS audio streams. The
8
CDB4923 CDB49300
Digital Input Digital Output
CS4340 CS8404A CS8404A CS8404A
+2.5V
CS8414
+3.3V
CS4340
Analog Output
RESET
CRD4923-MEM CDB49300-MEM
CS492x CS493xx
CS4340
Control Interface
PLL
PLD
Stereo Analog In
CS5334 OSC
Patch Area
Figure 1. External Memory Example
input ports of the DSP. These configuration allows the user to drive signals on stake headers J11 and J12 in order to operate the DSP as if it were part of an embedded system. The user is responsible for providing the appropriate clocking signals, control signals, and data signals to the DSP in full external mode, but the user only provides control signals in exernal control mode. In the external modes the audio output of the DSP still drives the on-board DACs and digital transmitters thus allowing the user to access the audio on the analog and digital output connectors provided by the CDB4923/300. The stake headers J11 and J12 can be found in Figure 4. All on-board clocks and data lines are routed through the PLD (U11) in order to provide maximum flexibility in the evaluation of different system configurations. The PLD will perform all +5 V to +3.3 V/+2.5 V conversions between the DSP and the +5 V parts with which it interacts by configuring the I/O power jumper (J63). The system can also be configured in an external interface described above. The external modes are detailed in Data Selection. All PLD modes are selected using
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DIP switch S3. The PLD (U11) and switch S3 are shown in Figure 7. A specialized IC (U12), the MAX708, has been included on the CDB4923/300 in order to generate a system reset at power-up, when the digital power begins to fail, and when the system reset button (SW1) is depressed. This chip helps to insure consistent operation on the board by providing a 200 ms reset pulse whenever activated.
5. DATA SELECTION
Data selection on the CDB4923/300 refers to the routing of audio data, audio clocks, control data, and control clocks. Because the PLD plays such a crucial role in determining the routing and control scheme, each data selection mode is also referred to as a `PLD mode.' It is important to note that Table 2, the PLD Mode table, is based directly upon the version of the control PLD (U11) used on each particular board. Each PLD has a specific revision code printed on its label. If your PLD version differs from the one described in this document, contact the factory to determine which feature set is provided with your board.
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CDB4923 CDB49300
The two major PLD modes for the CDB4923/300 are the PROVIDED resource mode and the EXTERNAL interface mode. When a PROVIDED mode is chosen all clocks are provided by the demonstration board, all audio data passes through the PLD, and the DSP is controlled by the PC parallel port interface. The EXTERNAL interface modes allow the user to drive the audio data and control pins of the DSP directly by wire-wrapping to stake headers J11 and J12, bypassing the control PLD. It should be noted that there are two variants of the EXTERNAL interface mode. One EXTERNAL mode provides direct access to all control and audio data input pins of the CS492x/CS493xx, and the second EXTERNAL mode allows the user to drive the control signals of the CS492x/CS493xx while audio data still comes from the CDB4923/300. The DIP switch S3 is used to choose the different routing schemes, and can be found in the Control schematic of Figure 7. Table 2 provides a general overview of the available PLD modes.
5.1
Provided Mode
When the user has chosen a PROVIDED resource mode, the PLD Mode determines the source of audio data for the two data pins of the DSP (CMPDAT--pin 27 and SDATAN1--pin 22) and the source of the system's oversampling clock (MCLK). Table 3 lists the routing configurations for each of the PROVIDED data selection modes.
5.1.1
Control
As mentioned earlier, when a PROVIDED mode has been selected, all control of the CDB4923/300 is accomplished using the parallel port (J29). A floppy disk is included with the CDB4923/300 which contains the control software described in Appendix F: Board Control Software.
5.1.2
Data
All of the Data Selection Modes shown in Table 3 imply PC control. In Table 4, a brief description is given for each data source listed in Table 3. The general data flow of the system is illustrated in Figure 2. A data path is shown for each of the modes listed in Table 3.
PLD Mode 0 1 2 3 4 5 6 7
DATA_SEL2 LO LO LO LO HI HI HI HI
DATA_SEL1 LO LO HI HI LO LO HI HI
DATA_SEL0 LO HI LO HI LO HI LO HI
AUDIO DATA, CONTROL, CONTROL SOURCE and CLOCKS EXTERNAL J11 EXTERNAL CONTROL J11 ONLY PROVIDED PC PROVIDED PC PROVIDED PC PROVIDED PC RESERVED RESERVED
NOTE: Because each mode of the Data Selection switch (S3) sets up a different hardware configuration, clock and data lines may be momentarily directed to many different destinations during mode changes. Without the proper initialization process after a reconfiguration, strange behavior may be observed. The recommended procedure for performing changes to the routing configuration is to first generate a board reset using the BOARD RESET switch (SW1). The CS492x/CS493xx will then require a soft reset ("CDB30RST.EXE -s" which performs a hardware reset and then sends the soft reset message 0x000001) and the proper hardware and application configuration messages for the new mode. A thorough description of soft reset, hardware configuration, and application configuration can be found in the software Application Notes AN115, AN120-123, AN140 or AN161-163. Table 2. Data Selection Modes (PLD version AB-X) 10 DS262DB2
CDB4923 CDB49300
CS4340 XMT958 CS8404A CS8404A CS8404A
CS4340 CS8414 CS8414 Data XMT958
CS4340 CDI
DAI Parallel Compressed Data
CS492x CS493x x
Stereo PCM
PCM Out
CS5334
Figure 2. CDB4923/300 Data Paths
PLD Mode 2 3 4 5
DATA_SEL2 LO LO HI HI
DATA_SEL1 HI HI LO LO
DATA_SEL0 LO HI LO HI
CS492x/CS493xx CMPDAT PC S/PDIF -- CS8414 S/PDIF -- CS8414 A/D -- CS5334
CS492x/CS493xx SDATAN1 A/D -- CS5334 S/PDIF -- CS8414 A/D -- CS5334 A/D -- CS5334
MCLK SOURCE DSP CS8414 CS8414 OSC/PLL
Table 3. PROVIDED Data Selection Modes (PLD version AB-X)
Digital Audio Source S/PDIF - CS8414 A/D - CS5334 PC
Description The CS8414 (U13) delivers the payload from an IEC60958 (linear PCM) or IEC61937 (nonlinear PCM) encoded bit-stream. The incoming S/PDIF stream is connected to either J32 or J30. The CS5334 (U25) delivers stereo PCM which has been encoded from the analog input signals on J55 and J56. A compressed digital audio stream is delivered in bursty format to the parallel port of the CS492x/CS493xx from a file on the PC. This transfer mode requires that the CDB4923/300 is in a parallel communication mode, and the PARLLPLY.EXE program is then used to deliver compressed data through the PC interface. NOTE: This data source is valid only for compressed audio and can be used only with parallel communication modes (i.e. INTEL or Motorola mode).
Table 4. Digital Audio Sources
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CDB4923 CDB49300
5.1.3 Audio Clocking 5.2 External Mode
The audio clocking scheme is illustrated below in Figure 3. Note that MCLK is bidirectional with respect to the DSP. When the DSP is slaved to an external MCLK, i.e. the MCLK source is not listed as DSP, the DSP will slave to the MCLK of the CS8414 or the MCLK derived from the on-board PLL (U26) or the OSCILLATOR (Y1). When the internal PLL of the CS492x/CS493xx is being used, however, the DSP will master the MCLK. Caution must be observed when choosing a particular data selection mode and configuring the DSP to ensure that there is no contention with the PLD (U11). Each PLD mode given in Table 3 lists the associated MCLK master - this table should be referenced whenever reconfiguring the CDB4923/300. A brief description of each MCLK source is given in Table 5.
MCLK Source CS8414 Description The CS8414 (U13) derives the sampling frequency (Fs) from an incoming S/PDIF stream and masters a 256 Fs MCLK The DSP (U1) masters MCLK, generally when using broadcast application code The source of the main DSP clock also supplies the system 256 Fs MCLK (see Clocking for details)
The EXTERNAL mode is designed to allow users to drive the DSP directly with an external microcontroller. Stake headers J11 and J12 contain all of the signals required for host communication with the CS492x/CS493xx. When operating in this mode the DSP control pins are tri-stated by the PLD (U11), effectively disabling the PC interface. Consequently, the software bundled with the demo board will not be functional. The main DSP clock is always provided by the CDB4923/300 (please see the Clocking section to determine how to select the oscillator or external PLL), and the output signals AUDATA0-2 are still routed to the CS8404A S/PDIF transmitters and CS4340 DACs. Depending on the EXTERNAL mode selected the user may be responsible for all data, control, and clock signals going to the DSP, or just control.
NOTE: ALL SIGNALS DRIVEN TO THE CS493xx MUST BE +3.3 V LOGIC. Because the CS493xx does not have +5 V tolerant pads, an external buffer such as the 74VHC244 should be used for level conversion of any signals driven to the DSP. Failure to buffer +5 V signals can cause permanent damage to the DSP. If necessary, level shifting buffers can be wired into the digital patch area of the CDB49300.
DSP OSC/PLL
Table 5. Clocking Descriptions
CS4340 CS8404A CS8404A CS8404A DIGITAL MCLK / ANALOG MCLK CS8414
CS4340
CS8414 MCLK CS4340 DSP MCLK DSP SCLK DSP LRCLK
CS492x CS493xx
CS5334
DIGITAL SCLK / ANALOG SCLK PLL OSC DIGITAL LRCLK / ANALOG LRCLK
Figure 3. Audio Clocking 12 DS262DB2
CDB4923 CDB49300
As mentioned above, many of the PLD's I/O pins are tri-stated. The complete list of tri-stated pins for full external mode (PLD Mode 0) can be found in Table 6. The complete list of tri-stated pins for external control mode (PLD Mode 1) can be found in Table 7. By design, the clocking signals present at the MCLK, LRCLK, and SCLK pins of the CS492x/CS493xx are used to drive both the audio input and output circuitry for the rest of the CDB4923/300 as shown in Figure 3. This means that the S/PDIF input, S/PDIF output, analog output and analog input continue to function in the EXTERNAL modes. The user should only drive audio clocks in PLD Mode 0. PLD Mode 1 derives audio clocks from the CS8414. The three clocking configurations that the user should be aware of when using PLD Mode 0 are: * * * DSP is slave to all audio clocks - user drives MCLK/SCLK/LRCLK DSP masters LRCLK/SCLK - user drives MCLK DSP masters MCLK/LRCLK/SCLK - user drives no audio clocks
Pin Name MCLK CMPCLK CMPREQ CMPDAT SCLKN1 SLRCLKN1 SDATAN1 RESET RD WR EXTMEM Pin Number 44 28 29 27 25 26 22 36 5 4 21 Pin Name DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 A1, CDIN A0, SCCLK SCPDIO CS Pin Number 17 16 15 14 11 10 9 8 6 7 19 18
Pin Name RESET RD WR A1, CDIN A0, SCCLK SCPDIO CS
Pin Number 36 5 4 6 7 19 18
Pin Name DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
Pin Number 17 16 15 14 11 10 9 8
Table 7. DSP Pins Tri-Stated by U11 in PLD Mode 1
MCLK Description Source J12 The user must provide an oversampling clock on the 23MCLK pin of stake header J12. (NOTE: This clock signal must be +3.3 V logic when using CS493xx) CS8414 The CS8414 (U13) derives the sampling frequency (Fs) from an incoming S/PDIF stream and masters a 256 Fs MCLK DSP The DSP (U1) masters MCLK, generally when using broadcast application code
Table 8. Clocking Descriptions
Only when the correct clocking is present on the 23MCLK, 23LRCLK, and 23SCLK pins (J12), processed audio can be heard on the analog outputs (J13 - J20) and the digital outputs (J45 - J47). The analog outputs J13-J20 can be found in Figure 12, and the digital outputs can be found in Figure 13. The information in Table 9 summarizes the operation of switch S3. The table shows the data routing configuration, the MCLK source, and the method of board control. This is intended as a quick reference and can also be found in Appendix J: Switch Summary.
Table 6. DSP Pins Tri-Stated by U11 in PLD Mode 0
DS262DB2
13
CDB4923 CDB49300
6. CLOCKING
There are four major clocks routed across the CDB4923/300: CLKIN for the DSP, MCLK, LRCLK, and SCLK. CLKIN is only used to drive the digital logic of the DSP core. MCLK, LRCLK, and SCLK are used for synchronizing the audio systems of the CDB4923/300. Since the PLL (U26) and the OSCILLATOR (Y1) are co-dependent, only one can be used at any given time. Jumper J37 is used to select the source of the main DSP clock. It is vital to note that the jumper J37 is a double jumper with two jumpers which must be moved in unison. If the jumpers are not moved together, board behavior will be unpredictable. Table 11 lists the oscillator requirements, and the two different settings for J37, where pins 3 and 4 are connected to the inputs of the PLD. Jumper J37 can also be found in Figure 8. In order to use the 27 MHz oscillator directly, Y1 should be populated with the 27 MHz oscillator included with the CDB4923/300 package. AdditionClock Source Oscillator Y1 27 MHz or 12.288 MHz oscillator 27 MHz oscillator J37 - Pin 3 J37 - Pin 4 OSC OSC
6.1
DSP Clock
The DSP clock of the CS492x/CS493xx is provided at the CLKIN pin (pin 30). The setting of jumper J1 (DSP CLOCK) determines whether the CS492x/CS493xx uses the input clock as the DSP clock directly (CLKIN position) or uses the input clock as a reference for the internal PLL (PLL position). There are two possible clock sources on the CDB4923/300. The first is the OSCILLATOR (Y1). The second option is the external PLL (U26) which can be configured to provide a processor clock ranging from 33 MHz to 81 MHz. All clocking circuitry can be found in Figure 8.
External PLL
PLL
PLL
Table 11. Board Clocking Configurations (J37)
PLD Mode 0 1 2 3 4 5 6 7
DATA SEL2 LO LO LO LO HI HI HI HI
DATA SEL1 LO LO HI HI LO LO HI HI
DATA SEL0 LO HI LO HI LO HI LO HI
CS492X/CS493XX CMPDAT S/PDIF -- CS8414 PC S/PDIF -- CS8414 S/PDIF -- CS8414 A/D -- CS5334
CS492X/CS493XX SDATAN1 A/D -- CS5334 A/D -- CS5334 S/PDIF -- CS8414 A/D -- CS5334 A/D -- CS5334 RESERVED RESERVED
MCLK MASTER J12 or DSP CS8414 DSP CS8414 CS8414 OSC/PLL
CONTROL SOURCE J11 & J12 J11 & J12 PC PC PC PC
Data and Control lines accessed via J11 and J12
Table 9. Data Selection Modes (Switch S3, PLD Version AB-X)
PLD Mode 0 1 DATA_SEL2 LO HI DATA_SEL1 LO HI DATA_SEL0 LO HI CS492x/CS493xx CMPDAT J12 S/PDIF -- CS8414 CS492x/CS493xx SDATAN1 J12 A/D -- CS5334 MCLK SOURCE J12 or DSP CS8414
Table 10. EXTERNAL Data Selection Modes (PLD Version AB-X)
14
DS262DB2
CDB4923 CDB49300
ally, both jumpers of J37 should be set to the OSC position. In this clocking configuration you should not use any modes which list OSC/PLL as the MCLK source while Y1 is 27 MHz. In order to use the 12.288 MHz oscillator directly, Y1 should be populated with the 12.288 MHz oscillator included with the CDB4923/300 package, and both jumpers of J37 should be set to the OSC position. The 12.288 MHz oscillator can be used with those PLD modes naming OSC/PLL as the MCLK source, as 12.288 MHz is a standard 256Fs oversampling frequency (256 * 48 kHz). The choice of 12.288 MHz or 27 MHz is application code dependent. Applications dealing with IEC61937 packed compressed audio generally require a 12.288 MHz input, while broadcast applications typically require a 27 MHz input. Check the relevant application code user's guide (AN120AN123, AN140 or AN161-AN163) for details on DSP CLKIN frequency. If the external PLL is to be used, then Y1 must be populated with a 27 MHz oscillator. The jumpers of J37 should both be placed in the PLL position. The CLKIN pin of the DSP will now be driven with the processor clock (PCLK) output of U26. The processor clock (PCLK) output can be configured to generate either a many different frequencies, based upon the configuration of jumpers J67, J68, and J72 as listed in Table 12. When using the external PLL to generate the DSP clock, the CLKSEL pin (J1) of the CS492x/CS493xx is typically set to `EXT CLK'. modes can select between an MCLK which is simply the frequency of the on-board oscillator (Y1), or a programmable MCLK generated by the external PLL (U26). The source of MCLK is dependent upon the PLD mode and is indicated by the `MCLK SOURCE' column of Table 9 and Table 24. U26 is a discrete PLL which can generate many different audio frequencies in addition to the processor clock discussed above. The frequency of the audio clock is controlled by the states of the AS1 and AS0 pins which are set with jumpers J70 and J71. The available audio clock frequencies can be used to support many different sampling frequencies, depending on the desired MCLK ratio. Table 13 enumerates all possible MCLK frequencies for the external PLL.
6.3
LRCLK and SCLK
LRCLK and SCLK are assumed to be generated by the DSP in all cases. The audio clocking diagram shown in Figure 3, illustrates the clocking scheme of the CDB4923/300. If it is necessary to provide a complete slave mode for the DSP, please contact the factory for details on how to properly configure the CDB4923/300.
PCLK Frequency 33.33 MHz 54 MHz 66.66 MHz 80 MHz 32 MHz 81 MHz 50 MHz 40 MHz J72 LO LO LO LO HI HI HI HI J67 LO LO HI HI LO LO HI HI J68 LO HI LO HI LO HI LO HI
6.2
MCLK
The system MCLK on the CDB4923/300 can come from four different sources when using a PROVIDED mode. Some PLD modes use the MCLK generated by the CS8414 S/PDIF receiver (U13) when there is an incoming S/PDIF stream. In PLD mode 2, the DSP generates MCLK when it is decoding a compressed bit stream delivered by the PC. Some
DS262DB2
Table 12. PCLK Configurations
MCLK Frequency 24.576 MHz 12.288 MHz 11.2896 MHz 8.192 MHz AS1 (J70) 1 0 0 1 AS0 (J71) 1 0 1 0
Table 13. Audio Frequency Selection (J58) 15
CDB4923 CDB49300
7. INPUT 7.1 Analog Input
A stereo input is provided at RCA jacks J55 and J56. These inputs are designed to accept a full-scale signal of 2 Vrms. Each single-ended signal is converted to a differential 2 Vrms signal before being applied to the inputs of the CS5334 ADC. The CS5334 and its analog input buffers can be found in Figure 9. The CS5334's clock signals can be accessed at the test points labeled ALG_MCLK, ALG_SCLK, and ALG_LRCLK (these test points can be found in Figure 11). The serial data stream coming from the CS5334 can be probed at the 34SDATA test point (TP22). Jumper J52 is used to configure the CS5334 for slave or master mode. The default, slave mode, is used when the CS5334 accepts all clock signals from another source. When in master mode, the CS5334 accepts MCLK and generates SCLK and LRCLK. The CDB4923/300 is configured to use the CS5334 in slave mode only. Please contact the factory for details on how to use the CS5334 in master mode. The digital output format of the CS5334 can be configured with switch S4 as described in Table 14. More details on the CS5334 can be found in the CS5334 datasheet. PARLLPLY.EXE program found on the included floppy. Audio delivered across the S/PDIF interface comes from a digital source such as a DVD player. The S/PDIF inputs are J30 (RCA) and J32 (Optical), and can be found in Figure 10. It is vital to note, though, that only one of these S/PDIF inputs can be used at any given time. The active jack is determined by the setting of jumper J31 (S/PDIF IN). When J31 is in the 'OPT' position, S/PDIF data will be accepted only from J32. When J31 is in the 'RCA' position, S/PDIF data will be accepted only from J30. The S/PDIF signal is routed to the CS8414 receiver (U13). The digital output format of the CS8414 is configured using switch S1 as described in Table 15. The CDB4923/300 comes from the factory configured to operate in I2S mode. Note that this default should not be changed unless the DSP has been configured to use a different serial format. Jumpers J65 and J66 control the SEL and CS12/FCK pins of the CS8414. These pins can be used to select what is displayed on the channel status outputs of the Digital Audio Interface Receiver. By default these pins are pulled up and the jumpers are not stuffed. If the user wishes to change the values of these pins a stake header should be installed. The CS8414, its control switch, and jumpers can be found in Figure 10. If more details on the CS8414 are needed, please reference the CS8414 datasheet.
7.2
Digital Input
There are two possible sources of digital audio for the CDB4923/300: S/PDIF, and bursty delivery from the host PC across the parallel interface. Bursty delivery is accomplished by spooling a file from the host PC to the CDB4923/300 using the
34DIF1 LO LO HI HI 34DIF0 Digital Input Format LO 20-Bit Left Justified, Rising SCLK HI 20-Bit Left Justified, Falling SCLK LO 20 Bit I2S, Rising SCLK (default) HI Power Down
M2 LO LO LO LO HI HI HI HI
M1 LO LO HI HI LO LO HI HI
M0 LO HI LO HI LO HI LO HI
Audio Serial Port Format Out, L/R, 16-24 Bits In, L/R, 16-24 Bits Out, L/R, I2S In, L/R, I2S (default) Out, WSYNC, 16-24 Bits Out, L/R, 16 Bits LSBJ Out, L/R, 18 Bits LSBJ Out, L/R, MSB Last
Table 14. CS5334 Digital Output Formats (S4)
Table 15. Digital Output Format settings for CS8414 (S1)
16
DS262DB2
CDB4923 CDB49300
8. OUTPUT 8.1 Analog Output
The six discrete outputs provided on the CDB4923/300 are driven by CS4340 D/A converters. They can be found at RCA jacks J13-J16, J18, and J20. Each output is driven directly by the CS4340 to provide a 3.5 Vpp full scale output. The CS4340 and its control signals can be found in Figure 11, and the analog output buffers can be found in Figure 12. The digital input format of the CS4340 is configured using switch S4. The CDB4923/300 is shipped with the CS4340 in I2S mode, and should not be changed unless the CS492x/CS493xx has been configured to use a different serial format. The list of data formats for the CS4340 can be found in Table 16. For more details on the features of the CS4340, please reference the CS4340 datasheet. down, and during audio clock discontinuities if the reset period is violated.
8.3
Digital Output
The signals present on analog outputs J13-J16, J18, and J20 can also be found on the digital outputs J45-J47 (AOUTDIG0-AOUTDIG2). The optical transmitters are driven by CS8404A S/PDIF transmitters (U19-21). The CS8404As are configured to operate in consumer mode by default. The mode of operation and status bits can be controlled by installing a 16 pin header in J44 and placing jumpers on the signals that are to be programmed low. All signals on J44 are pulled up by default. The CS8404A transmitters and optical outputs can be found in Figure 13. The digital input format of the S/PDIF transmitters can be controlled with switch S2 as listed in Table 17. More operational details for the CS8404A can be found in the CS8404A datasheet. Optical transmitter J43 (XMT958) is directly connected to the S/PDIF transmitter of the DSP. It can be used to directly observe the digital output of the CS492x/CS493xx when the application code running on the part utilizes the transmitter. Note that if the application code does not support S/PDIF transmission, J43 will not generate valid data. Please see the application note associated with the code in question (e.g. AN120-123, AN140, or AN161AN163) to determine whether J43 should be active.
8.2
Analog Output Protection Circuitry
The CS4340 is designed to perform a `soft' ramping of the bias voltage in order to prevent popping on the outputs. However, the series capacitance found in the analog buffers of the CS4340 require a finite amount of time to discharge when the CS4340 goes into reset (RC time constant). If the full reset period is not observed before new audio is delivered, popping can occur on the outputs. Please see the CS4340 datasheet for more details. The four transistors connected to the mute output of each CS4340 are used to ensure that no 'popping' will occur on the outputs during power-up, power-
27DIF1 LO LO HI HI
27DIF0 LO HI LO HI
Digital Input Format 16-24 Bit I2S (default) 16-24 Bit Left Justified 24-Bit Right Justified 16-Bit Right Justified
M2 LO LO LO LO HI HI HI HI
M1 LO LO HI HI LO LO HI HI
M0 LO HI LO HI LO HI LO 1
Audio Serial Port Format FSYNC & SCK Output Left/Right, 16-24 Bits Word Sync, 16-24 Bits Reserved Left/Right, I2S (default) LSB Justified, 16 Bits LSB Justified, 18 Bits MSB Last, 16-24 Bits
Table 16. CS4340 Digital Input Formats (S4)
Table 17. Digital Input Format settings for CS8404A (S2)
DS262DB2
17
CDB4923 CDB49300
9. APPENDIX A: SCHEMATICS
18
DS262DB2
Figure 4. CS492x/CS493xx
CDB4923 CDB49300
DS262DB2
Figure 5. System Power
19
CDB4923 CDB49300
20
Figure 6. PC Interface DS262DB2
CDB4923 CDB49300
DS262DB2
Figure 7. Control Logic
21
CDB4923 CDB49300
22
Figure 8. Clocking DS262DB2
CDB4923 CDB49300
DS262DB2
Figure 9. Analog Input 23
CDB4923 CDB49300
24
Figure 10. Digital Input DS262DB2
CDB4923 CDB49300
DS262DB2
Figure 11. D/A Converters 25
CDB4923 CDB49300
26
DS262DB2
Figure 12. Analog Output
CDB4923 CDB49300
DS262DB2
Figure 13. Digital Output 27
CDB4923 CDB49300
28
DS262DB2
Figure 14. Top Layer
CDB4923 CDB49300
DS262DB2
Figure 15. Bottom Layer 29
CDB4923 CDB49300
30
DS262DB2
Figure 16. SSTOP
CDB4923 CDB49300
DS262DB2
Figure 17. ASYSTOP 31
CDB4923 CDB49300
32
DS262DB2
Figure 18. Layer 2
CDB4923 CDB49300
DS262DB2
Figure 19. Layer 3
33
34 DS262DB2
10. APPENDIX D: BILL OF MATERIALS
Item Quan Reference 1 15 C1,C7,C8,C9,C91,C96,C101,C129,C132,C15 9,C160,C163,C164,C167,C168 2 42 C4,C10,C11,C12,C66,C67,C68,C69,C71,C72, C90,C95,C100,C106,C107,C108,C109,C110, C111,C112,C130,C133,C138,C139,C141,C14 3,C149,C150,C151,C152,C153,C157,C161,C 162,C165,C166,C169,C170,C172,C174,C175, C176 3 6 C18,C24,C28,C36,C41,C48 4 12 C19,C20,C25,C26,C29,C30,C37,C38,C42,C4 3,C49,C50 5 3 C51,C55,C148 6 5 C56,C156,C158,C171,C173 7 1 C57 8 8 C58,C59,C60,C61,C62,C63,C64,C65 9 3 C73,C75,C76 10 1 C74 11 1 C113 12 3 C119,C122,C134 13 2 C128,C120 14 2 C131,C121 15 2 C140,C142 16 1 C154 17 1 C155 18 5 D2,D3,D4,D5,D6 19 2 FB5,FB2 20 13 J1,J2,J3,J31,J52,J62,J63,J67,J68,J69,J70,J71 ,J72 21 2 J11,J12 22 1 J37 23 1 J44 24 4 J59,J60,J65,J66 25 1 J64 26 9 J13,J14,J15,J16,J18,J20,J30,J55,J56 27 1 J21 28 2 J24,J22 29 1 J23 Part Number T491B105M035AS C1206C104K5RAC Manufacturer KEMET KEMET Description CAP, 1UF, TANT, 3528, 35V, 10% CAP, .1UF, X7R, 1206, 50V, 10%
T491B335K020AS C1206C152F5GAC T491D476M020AS T491C476M010AS C1206C474K3RAC C1206C224K5RAC C1206C103K5RAC 12062R683K9BB2 1206CG471J9BB2 T491C106K020AS C1206C100J5GAC C1206C222J5GAC C1206C470J5GAC C340C225K5R5CA C330C103K5R5CA LN1351C-TR 542-FB43-226 TSW-103-07-G-S TSW-110-07-G-D TSW-103-07-G-D TSW-108-07-G-D TSW-102-07-G-S TSW-111-07-G-S 16PJ097 111-0110-001 111-0103-001 111-0102-001
KEMET KEMET KEMET KEMET KEMET KEMET KEMET PHILIPS PHILIPS KEMET KEMET KEMET KEMET KEMET KEMET PANASONIC MOUSER SAMTEC SAMTEC SAMTEC SAMTEC SAMTEC SAMTEC MOUSER JOHNSON COMPONENTS JOHNSON COMPONENTS JOHNSON COMPONENTS
CAP, 3.3UF, TANT, 3528, 20V, 10% CAP, 1500PF, COG, 1206, 50V, 1% CAP, 47UF, TANT, 7343, 20V, 20% CAP, 47UF, TANT, 6032, 20V, 20% CAP, .47UF, X7R, 1206, 25V, 10% CAP, .22UF, X7R, 1206, 50V, 10% CAP, .01UF, X7R, 1206, 50V, 10% CAP, .068UF, X7R, 1206, 50V, 10% CAP, 470PF, COG, 1206, 50V, 5% CAP, 10UF, TANT, 6032, 20V, 10% CAP, 10PF, COG, 1206, 50V, 5% CAP, 2200PF, COG, 1206, 50V, 5% CAP, 47PF, COG, 1206, 50V, 5% CAP, 2.2UF, X7R, C340, 50V, 10% CAP, .01UF, X7R, C330, 50V, 10% LED, GREEN, 3216 INDUCTOR, FERRITE BEAD STAKE HEADER, 3X1, .1"CENTER, GOLD STAKE HEADER, 10X2, .1"CENTER, GOLD STAKE HEADER, 3X2, .1" CENTER, GOLD STAKE HEADER, 8X2, .1" CENTER, GOLD STAKE HEADER, 1X2, .1"CENTER, GOLD STAKE HEADER, 11X1, .1"CENTER, GOLD CONNECTOR, RCA, RA, GOLD BINDING POST, BLUE BINDING POST, BLACK BINDING POST, RED
CDB4923 CDB49300
Item 30 31 32 33 34 35 36 37 38 39 40 41 42
Quan 1 1 1 4 1 3 3 6 2 1 1 1 37
43 44
3 38
45 46 47 48 49 50 51 52 53 54 55 56 57 58
6 3 5 5 2 1 1 1 4 4 2 1 6 1
Reference J57 J29 J32 J43,J45,J46,J47 L1 Q1,Q5,Q9 Q2,Q6,Q10 Q3,Q4,Q7,Q8,Q11,Q12 RP5,RP1 RP2 RP3 RP4 R1,R2,R49,R54,R59,R66,R74,R80,R112,R120 ,R150,R151,R152,R153,R160,R161,R163,R1 64,R184,R185,R186,R192,R193,R194,R212, R214,R216,R222,R224,R233,R235,R242,R24 8,R249,R256,R257,R258 R6,R196,R197 R14,R17,R19,R24,R26,R28,R31,R34,R36,R4 1,R87,R88,R89,R90,R91,R92,R94,R96,R98,R 100,R102,R103,R104,R105,R106,R107,R110, R126,R129,R130,R131,R190,R191,R198,R20 0,R239,R240,R241 R50,R55,R60,R67,R75,R81 R84,R85,R226 R86,R210,R217,R220,R229 R109,R119,R156,R169,R173 R114,R225 R117 R118 R155 R175,R187,R188,R189 R211,R221,R232,R247 R218,R228 R246 R250,R251,R252,R253,R254,R255 R259
Part Number Manufacturer 111-0104-001 JOHNSON COMPONENTS 747238-4 AMP TORX173 TOSHIBA TOTX173 TOSHIBA 43LS475 MILLLER MMUN2111LT1 MOTOROLA MMUN2211LT1 MOTOROLA 2SC2878 TOSHIBA 4610X-101-103 BOURNS 4606X-101-102 BOURNS 4610X-101-102 BOURNS 4606X-101-103 BOURNS CRCW12061002FT DALE
Description BINDING POST, GREEN CONNECTOR, D-SUB, 25-PIN, MALE, RA OPTICAL TOSLINK RECIEVER OPTICAL TRANSMITTER INDUCTOR, 47UF TRANSISTOR, PNP, SOT-23 TRANSISTOR, NPN, SOT-23 TRANSISTOR, TO-92 RES NETWORK, 10K-OHM, 10-PIN, BUSSED RES NETWORK, 1K-OHM, 6-PIN, BUSSED RES NETWORK, 1K-OHM, 10-PIN, BUSSED RES NETWORK, 10K-OHM, 6-PIN, BUSSED RES, 10K-OHM, 1206, 1%, 1/8W, METAL FILM
DS262DB2 35
CRCW1206472JT CRCW1206330JT
DALE DALE
RES, 4.7K-OHM,1206, 5%, 1/8W, METAL FILM RES, 33-OHM, 1206, 5%, 1/4W, METAL FILM
CRCW12065610FT CRCW12061001FT CRCW1206151JT CRCW1206000ZP CRCW12062R0JT CRCW12064750FT CRCW1206750JT CRCW12063320FT CRCW12061782FT CRCW12064752FT CRCW1206203JT CRCW12063302FT CRCW1206202JT CRCW1206510JT
DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE DALE
RES, 560-OHM, 1206, 1%, 1/4W, METAL FILM RES, 1K-OHM, 1206, 1%, 1/8W, METAL FILM RES, 150-OHM, 1206, 5%, 1/8W, METAL FILM RES, 0-OHM, 1206, 1%, 1/8W, METAL FILM RES, 2-OHM, 1206, 5%, 1/8W, METAL FILM RES, 470-OHM, 1206, 1%, 1/4W, METAL FILM RES, 75-OHM, 1206, 5%, 1/4W, METAL FILM RES, 330-OHM, 1206, 1%, 1/8W, METAL FILM RES, 17.8K-OHM, 1206, 1%, 1/8W, METAL FILM RES, 47K-OHM, 1206, 1%, 1/8W, METAL FILM RES, 20K-OHM, 1206, 5%, 1/8W, METAL FILM RES, 33K-OHM, 1206, 1%, 1/8W, METAL FILM RES, 2K-OHM, 1206, 5%, 1/4W, METAL FILM RES, 51-OHM, 1206, 5%, 1/4W, METAL FILM
CDB4923 CDB49300
36 DS262DB2
Item 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
Quan 1 3 1 14 1 1 1 2 1 1 1 1 3 3 2 2 1 1 1 1 1 2 1 5 2 6 6 1
Reference SW1 S1,S2,S3 S4 TP5,TP17,TP18,TP19,TP20,TP21,TP22,TP23 ,TP24,TP25,TP26,TP27,TP28,TP29 U1 UX1 U8 U10,U9 U11 UX11 U12 U13 U16,U17,U18 U19,U20,U21 U23,U24 UX23,UX24 U25 U26 U27 Y1 YX1 Z1,Z4 Z2 J21,J22,J23,J24,J57 FB5,FB2 HARDWARE HARDWARE PCB
Part Number PT645TL50 76SB03 76SB04 TSW-101-07-G-S CS493001-CL 540-93-044-24-000 LM3940IT-3.3
Manufacturer C&K GRAYHILL GRAYHILL SAMTEC
Description SWITCH,PB,DPST,5 LEG DIP SWITCH, 3 POSITION DIP SWITCH, 4 POSITION STAKE HEADER, 1X1, .1"CENTER, GOLD
CRYSTAL MILL-MAX NATIONAL SEMICONDUCTOR DM74ALS541WM FAIRCHILD SEMICONDUCTOR EPM7128ALC84-12 ALTERA 540-99-084-24-000 MILL-MAX MAX708ACT MAXIM CS8414-CS CS4340-KS CS8404A-CS CRYSTAL SEMI. CRYSTAL
SOCKET-D.U.T. HOLE, PLCC-44, PIH +3.3V REGULATOR, TO-220 IC,OCTAL BUFFER/LINE DRIVER/LINE RECIEVER,SO20 INTEGRATED CIRCUIT, PLCC84 SOCKET, PLCC-84, PIH INTEGRATED CIRCUIT, SUPERVISORY CIRQUIT, INTEGRATED CIRCUIT, SOIC28 - WIDE INTEGRATED CIRCUIT, 24-bit, 96kHz DAC, 16pin SOIC INTEGRATED CIRCUIT, SOIC24 - WIDE INTEGRATED CIRCUIT, DUAL OP AMP, DIP-8 S0CKET, 300-MILL, DIP-8 INTEGRATED CIRCUIT, SSOP20 INTEGRATED CIRCUIT, VOLTAGE REGULATOR, +2.5V, TO-220
CRYSTAL SEMICONDUCTOR MC33078-P MOTOROLA 110-93-308-41-001 MILL-MAX CS5334-KS CRYSTAL SEMICONDUCTOR MK2744-10S MICRO-CLOCK LM2937ET-2.5 NATIONAL SEMICONDUCTOR CX21AF-27.000MHZ CAL CRYSTAL 110-93-314-41-001 MILL-MAX P6KE16A MOTOROLA P6KE6.8A MOTOROLA L1.50x.25TX.25T, SQUIRES TY PE E 24/19 C2015L-1000-ND DIGI-KEY 8F1943 NEWARK HD343-ND DIGI-KEY CDB4923/30 REV-A PROTECH
CDB4923 CDB49300
OSCILATOR,, 27.000MHZ, TTL/CMOS, DIP-14 S0CKET, 300-MILL, DIP-14 DIODE, ZENER, AXIAL, 13V, DO-15 DIODE, ZENER, AXIAL, 6.8V, DO-7 BINDING POST HOOK UP WIRES 24AWG/HOOK-UP/STRNED FOR FERRITE BEADS STANDOFFS SCREWS, 4/40, 1/4" PRINTED CIRCUIT BOARD
EXTMEM EMOE
D7 D5 D3 D1
R10
3X1HDR 74LVC125
D6 D4 D2 D0
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
0
1 2 3
U5A
uC15
2
1
U5B
4
uC15 U5C
9 10
C5
.1uF
8
14
3X1HDR 74LVC125
uC15 uC17 +3.3V
U5D
12 13
+3.3V
11
uC17
74LVC125
R1
10k
R8
0
1 2 3
3X1HDR
CDB4923 CDB49300
Figure 20. CRD4923-MEM Schematic
7
DS262DB2
uC17
U3
O0 O1 O2 O3 O4 O5 O6 O7 13 14 15 17 18 19 20 21
uC16
U1 U2
A15
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 11 CK VCC OE GND 1 20 10 19 18 17 16 15 14 13 12 2 3 4 5 6 7 8 9 19 18 17 16 15 14 13 12
A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7
A8 A9 A10 A11 A12 A13 A14
EXTMEM EMOE
R 1 3 10k R 1 4 10k
+3.3V EMOE
CK OE VCC GND VCC GND 20 10 11
DSP15 +3.3V
C2
.1uF
VPP 32 16 1
CE OE PGM
22 24 31
+3.3V
EMOE
1
C1
.1uF TC74VHC574FW
TC74VHC574FW
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 AT27LV02 0A-90JC
30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A7 A6 A5 A4 A3 A2 A1 A0
C3
.1uF
+3.3V
47uF
+
C7
A[0:14]
.1uF
C6
P1 uC16
+3.3V uC17 REQ23
3
MRESET23
A15 +3.3V
6
uC16 DSP15
5
+3.3V
74LVC125
11. APPENDIX E: EXTERNAL MEMORY SCHEMATICS
R9
0
1 2 3
U5E
R E Q 23
74LVC125
37
1
13
EMAD2 EMAD1 EMAD0
R15 R17 R18
49.9 49.9 49.9
VCC GND
1G DIR
#EXTMEM #EMWR
14
+3.3V
R19 0 C9
0.1uF
Figure 21. CDB49300-MEM Schematic
7
38
U1
EMAD[7:0]
EMAD0 EMAD1 EMAD2 EMAD3 EMAD4 EMAD5 EMAD6 EMAD7
U2
2 3 4 5 6 7 8 9 11 1 D0 D1 D2 D3 D4 D5 D6 D7 CK VCC OE GND Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12
A0 A1 A2 A3 A4 A5 A6 A7
A0 A1 A2 A3 A4 A5 A6 A7
U3
2 3 4 5 6 7 8 9 11 1 D0 D1 D2 D3 D4 D5 D6 D7 CK VCC OE GND Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12
A8 A9 A10 A11 A12 A13 A14 A15
A8 A9 A10 A11 A12 A13 A14 A15
U4
2 3 4 5 6 7 8 9 11 1 D0 D1 D2 D3 D4 D5 D6 D7 CK VCC OE GND Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12
A16
uC17 uC16 uC15
+3.3V
20 10
#EMOE
#EMOE
C1
0.1uF
20 10
+3.3V
C2
0.1uF
#EMOE
20 10
+3.3V
C3
0.1uF
74LVC574
74LVC574
74LVC574
A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
30 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12
A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A7 A6 A5 A4 A3 A2 A1 A0
O0 O1 O2 O3 O4 O5 O6 O7 CE OE PGM VPP VCC GND
13 14 15 17 18 19 20 21 22 24 31 1 32 16
D0 D1 D2 D3 D4 D5 D6 D7
D[7:0]
uC18 #EXTMEM #EMWR
R1
10K
+3.3V
C4
0.1uF
AT27LV020A
A[16:0] +3.3V uC18 +3.3V
C6 C7 P1
1 3 5 7 9 11 13 15 17 19
+3.3V
U6A
2
C5
0.1uF
3
47uF
+
#ABOOT
U5
A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
8 10 7 11 4 12 1 31 2 3 13 14 15 16 17 18 19 20 VCC A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE2 OE CE1 WE D7 D6 D5 D4 D3 D2 D1 D0 NC GND
R2
10K
6 32 30 5 29 28 27 26 25 23 22 21 9 24
0.1uF
74LVC125
#EXTMEM #uC18 #EMWR
D0 D1 D2 D3 D4 D5 D6 D7
uC17 uC15 #EXTMEM #EMOE
R3 R5 R7 R9
49.9 49.9 49.9 49.9
#RESET
EMAD6 EMAD4 EMAD2 EMAD0
2 4 6 8 10 12 14 16 18 20
R4 R6
EMAD7 EMAD5 EMAD3 EMAD1
49.9 49.9 49.9
#ABOOT uC18 uC16 #EMWR
+3.3V
U6D
12
R8
11
#uC18
R16
10K
74LVC125
D[7:0]
EMAD[7:0]
EMAD[7:0]
EMAD7 EMAD6 EMAD5 EMAD4 EMAD3
R10 R11 R12 R13 R14
49.9 49.9 49.9 49.9 49.9
U7
18 17 16 15 14 13 12 11 20 10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 A1 A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 19 1
D[7:0]
D7 D6 D5 D4 D3 D2 D1 D0 C8
0.1uF CY7C109V33
+3.3V
CDB4923 CDB49300
U6E
74LVC125
74VHC245
DS262DB2
CDB4923 CDB49300
12. APPENDIX F: BOARD CONTROL SOFTWARE
There is a suite of programs used to control the CDB4923/300. The definitions given refer to `CDB30' executables which should be used with the both the CDB4923 and the CDB300. These software tools are designed to operate from a DOS prompt and can work with any parallel port address (LPT1, LPT2, or LPT3). The default address for all of the programs is 0x378 (also known as LPT1), but the port address can be changed by using the '-p' option provided with every tool. Each time a program is executed, the address that was used is echoed to the screen. If a program seems to fail, verification of the parallel port address should the first step in troubleshooting. All of these programs are designed to access the CS492x/CS493xx using SPI or I2C serial communication, or INTEL or MOTOROLA parallel communication. The communication mode can be chosen from the command line with the '-m' option. It should be remembered that the mode chosen must correspond to the communication mode used by the CS492x/CS493xx. If the DSP is using a communication mode which does not match the software setting, results will be unpredictable. Please see Digital Signal Processor of this datasheet to learn how to change the DSP's communication mode. The source code for all programs can be found on the floppy disk provided with the CDB4923/300. These programs are documented and will provide insight into communicating successfully with the CS492x/CS493xx. The source for CDB30_LD is particularly useful since it demonstrates the full handshaking protocol required during boot-up of the CS492x/CS493xx.
CDB30_LD - program used to load code into the CS492x/CS493xx. Usage: cdb30_ld [-pXXX] [-mY] [-v] -p = parallel port address XXX = address (0x278, 378* or 3bc) -m = communication mode Y = mode designator (i = I2C*, s=SPI, m=MOT, n=INT) -v = disable verbose mode * = default CDB30CMD - program used to send commands, or configuration files to the CS492x/CS493xx. Usage: cdb30cmd <[ABCDEF] or [-fY]> [-mZ] [-pXXX] [-v] ABCDEF = Three byte hex command -f = send configuration file Y = .cfg file with configuration parameters -p = parallel port address XXX = address (0x278, 378* or 3bc) -m = communication mode Z = mode designator (i = I2C*, s = SPI, m=MOT, n=INT) -v = disable verbose mode DS262DB2 39
CDB4923 CDB49300
* = default EXAMPLES: cdb23cmd 000001 -p3bc cdb23cmd -fac3.cfg -mS -p3bc CDB30_RD - program used to read back responses from the CS492x/CS493xx. If the INTREQ pin is not low when CDB30_RD is executed, the program will wait until INTREQ drops. Press the `Enter' key to exit the read wait loop. Usage: cdb30_rd [-pXXX] [-mY] [-v] [-h] -p = parallel port address XXX = address (0x278, 378* or 3bc) -m = communication mode Y = mode designator (i = I2C*, s = SPI, m=MOT, n=INT) -v = disable verbose mode -h = this message * = default CDB30RST - program used to perform hard reset or soft reset on the CS492x/CS493xx. Usage: cdb30rst [-s] [-pXXX] [-mY] [-v] [-h] -s = Soft Reset -p = parallel port address XXX = address (0x278, 378* or 3bc) -m = communication mode Y = mode designator (i = I2C*, s = SPI, m=MOT, n=INT) -v = disable verbose mode -h = this message * = default PARLLPLY - program used to deliver compressed audio files to the parallel host port of the CS492x/CS493xx from the PC. Usage: parllply [-pXXX] [-mY] [-l] [-b] [-cNNN] -p = parallel port address XXX = address (0x278, 378* or 3bc) -l = Loop Mode -b = Byte Swap
40
DS262DB2
CDB4923 CDB49300
-m = Parallel control mode Y = n (INTEL) or m (MOTOROLA)* -c = Chunk Size NNN = transfer size in words (252*) * = default CDB30_AD - program used to demonstrate autodetection on the CDB4923/300 only with IEC61937 or IEC60958 input. This program will download new application code from the PC each time a format change has been detected. The user should specify `invalid' for any application code or configuration file which does not exist. This program only allows serial control. Usage: cdb30_ad [-pXXX] [-mY] [-v] Specify invalid for non-existent .ld/.cfg. -p = parallel port address XXX = address (0x278, 378* or 3bc) -m = communication mode Y = mode designator (i = I2C*, s = SPI) -v = disable verbose mode * = default EXAMPLE: cdb30_ad ac3_263b.ld ac3_ad.cfg invalid invalid dts_2637.ld dts_ad.cfg ac3_263b.ld pcm_ad.cfg -p3bc -ms
DS262DB2
41
CDB4923 CDB49300
13. APPENDIX G: IC COMPONENT LISTING BY FUNCTION
13.1 POWER
U8 U27 3.3 V Voltage Regulator {Figure 5} 2.5 V Voltage Regulator {Figure 5}
13.2
RESET
U12 MAX708 Reset chip {Figure 7}
13.3
CLOCKING
U26 Y1 MK2744 Programmable Phase Locked Loop (PLL) {Figure 8} Oscillator {Figure 8}
13.4
SIGNAL ROUTING/LEVEL CONVERSION
U11 EPM7128E Programmable Logic Device {Figure 7}
13.5
DSP
U1 CS492x/CS493xx Multi-Channel Audio Decoder {Figure 4}
13.6
INPUT
U9 U10 U13 U23 U24 U25 Signal Buffer for Parallel Port {Figure 6} Signal Buffer for Parallel Port {Figure 6} CS8414 S/PDIF receiver {Figure 10} MC33078 Analog Input Buffer {Figure 9} MC33078 Analog Input Buffer {Figure 9} CS5334 20-bit A/D converter {Figure 9}
13.7
OUTPUT
U16 U17 U18 U19 U20 U21 CS4340 20-bit D/A converter {Figure 11} CS4340 20-bit D/A converter {Figure 11} CS4340 20-bit D/A converter {Figure 11} CS8404A S/PDIF transmitter {Figure 13} CS8404A S/PDIF transmitter {Figure 13} CS8404A S/PDIF transmitter {Figure 13}
42
DS262DB2
CDB4923 CDB49300
14. APPENDIX H: JUMPERS LISTED BY FUNCTION
14.1 AUDIO INPUT JUMPERS
J31 This jumper is used to select the input connector which is being used to receive S/PDIF data. Placing the jumper in the 'RCA' position enables the RCA jack, and placing the jumper in the 'OPT' position enables the TORX173 optical receiver. Default: OPT This jumper is used to control the MASTER/SLAVE clocking mode of the CS5334 as described in the CS5334 datasheet. This jumper should be left in the 'SLAVE' position when using the factory programmed PLD provided with the CDB4923/300. Default: SLAVE This jumper is used to control the SEL pin of the CS8414. This pin, in conjunction with J66, is used to select which channel status pin information to display on the status output pins. Please refer to the CS8414 datasheet for more details on how to configure the CS8414. Default: HI (Not Populated). This jumper is used to control the CS12/FCK pin of the CS8414. This pin, in conjunction with J65, is used to select which channel status pin information to display on the status output pins. Please refer to the CS8414 datasheet for more details on how to configure the CS8414. Default: HI (Not Populated).
J52
J65
J66
14.2
AUDIO OUTPUT JUMPERS
J44 This particular component is actually a set of jumpers. Each individual jumper can be used to control the state of one channel status bit in the outgoing S/PDIF stream created by the CS8404A. More details can be found in the datasheet for the CS8404A and the specifications for IEC60958 and IEC61937 bitstreams. Default: All bits HI {Not Populated}
14.3
DSP JUMPERS
J1 This jumper is used to control the internal clocking of the CS492x/CS493xx. When in the 'CLKIN' position, the CS492x/CS493xx uses the clock on the CLKIN pin to drive the DSP core directly. When in the 'PLL' position, the CS492x/CS493xx derives all internal clocks from the reference frequency provided at the CLKIN pin. Default: CLKIN This jumper selects the pull-up/pull-down state of the CS492x/CS493xx's WR pin. This jumper is used in conjunction with J3 and J62 to select the Host Interface Mode of the CS492x/CS493xx when it comes out of reset. By default the CDB4923/300 is configured for I2C serial communication. The settings for J2 (WR), J3 (RD) and J62 (PSEL) are detailed in the CS4923/4/5/6/7/8/9 datasheet and the CS49300 datasheet. Default: HI This jumper selects the pull-up/pull-down state of the CS492x/CS493xx's RD pin. This jumper is used in conjunction with J2 and J62 to select the Host Interface Mode of the CS492x/CS493xx when it comes out of reset. By default the CDB4923/300 is configured for I2C serial communication. The settings for J2 (WR), J3 (RD) and J62 (PSEL) are detailed in the CS4923/4/5/6/7/8/9 datasheet and the CS49300 datasheet. Default: LO Stake header providing some serial communication lines, and all general purpose I/O pins. This header is also serves as the memory interface to the CRD4923_MEM/CDB49300_MEM. This
J2
J3
J11
DS262DB2
43
CDB4923 CDB49300
header can be used to probe signals during normal operation, and may be used as a wirewrap point when using Data Selection Mode 0 or 1, as detailed in the Data Selection section of this datasheet. J12 Stake header providing access to all serial audio data and clock pins. This header can be used to probe signals during normal operation, and may be used as a wirewrap point when using Data Selection Mode 0 or 1, as detailed in the Data Selection section of this datasheet This jumper selects the pull-up/pull-down state of the CS492x/CS493xx's PSEL pin. When coming out of reset, the state of the PSEL pin determines which parallel interface mode to use (Motorola or Intel) when initializing the CS492x/CS493xx into a parallel host interface mode. This jumper is used in conjunction with J2 and J3 to select the Host Interface Mode of the CS492x/CS493xx when it comes out of reset. Because the PSEL pin has multiplexed functionality it also serves as SCDIO when in I2C mode. By default this jumper is in the 'HI' position since the board is initially configured for I2C serial communication and the SCDIO pin is open-drained. The settings for J2 (WR), J3 (RD) and J62 (PSEL) are detailed in the CS4923/4/5/6/7/8/9 datasheet and the CS49300 datasheet. Default: HI
J62
14.4
POWER JUMPERS
J59 This jumper connects DSP_PWR to the analog side of the CS492x/CS493xx. Analog current consumption can be measured by removing this jumper and connecting an ammeter in series with the jumper. Default: INSTALLED This jumper connects DSP_PWR to the digital side of the CS492x/CS493xx. Digital current consumption can be measured by removing this jumper and connecting an ammeter in series with the jumper. Default: INSTALLED This jumper is used to select the maximum voltage at which the I/O pins of the system PLD (U11) will drive its outputs. The user can select between +3.3 V and +2.5 V. Default: +3.3 V This jumper (DSP_PWR) is used to select the core voltage for DSP power. This jumper is provided to allow the user to evaluate both the CS4923/4/5/6/7/8 family and the CS49300 family of audio decoders. The CS4923/4/5/6/7/8 family requires +3.3 V, while the CS49300 family requires +2.5 V. The user can select between +3.3 V and +2.5 V. CDB4923 Default: +3.3 V CDB49300 Default: +2.5 V
J60
J63
J69
14.5
SYSTEM CLOCKING JUMPERS
J37 This dual position jumper select between an oscillator or the MK2744-10S discrete PLL (U26) as the external clock source for the DSP of the CS492x/CS493xx, and it also selects the system MCLK for non-S/PDIF input modes. It is important to note the jumpers of J37 must move together. They must be both in the 'OSC' position or they must both be in the 'PLL' position. Moving only one jumper will result in erratic behavior. When both jumpers are in the 'OSC' position, the CS492x/CS493xx CLKIN pin is driven by the oscillator, Y1, and some of the data modes chosen by switch S3 will provide a system MCLK which is also derived from Y1. Specifically, all data selection modes listed in Table 9 and Table 24 showing an MCLK Source of 'OSC/PLL' will generate a system MCLK equal to the frequency of the oscillator Y1. If you have questions about how to utilize the external PLL, please contact the factory before
44
DS262DB2
CDB4923 CDB49300
adjusting this jumper. Y1 must be a 27 MHz oscillator before attempting to use U26. When both jumpers are in the 'PLL' position, U26 will drive the CLKIN pin of the CS492x/CS493xx with the configured PCLK (refer to Table 12 or Table 22), and the system MCLK will be driven by ACLK. The frequency of MCLK can be programmed by changing the values of the AS1 and AS0 pins of U26 as detailed in Table 13 of this datasheet. Default: OSC OSC J67 Jumper used to set the value of the PS1 pin of U26. This jumper, in conjunction with J68 and J72, determines the processor clock frequency provided by the external PLL. Please refer to Table 12 or Table 22 for more details. Default: LO Jumper used to set the values of the PS0 pin of U26. This jumper, in conjunction with J67 and J72, determines the processor clock frequency provided by the external PLL. Please refer to Table 12 or Table 22 for more details. Default: HI Jumper used to set the values of the AS1 pin of U26. This jumper, in conjunction with J71, determines the MCLK frequency provided by the external PLL. Please refer to Table 13 for more details. Default: HI Jumper used to set the values of the AS0 pin of U26. This jumper, in conjunction with J70, determines the MCLK frequency provided by the external PLL. Please refer to Table 13 for more details. Default: 50 Jumper used to set the values of the PS2 pin of U26. This jumper, in conjunction with J67 and J68, determines the processor clock frequency provided by the external PLL. Please refer to Table 12 or Table 22 for more details. Default: LO
J68
J70
J71
J72
DS262DB2
45
CDB4923 CDB49300
15. APPENDIX I: JUMPERS LISTED BY NUMBER
NOTE: Each jumper listed below is described in Appendix H: Jumpers Listed by Function. The relevant section heading is listed beside each jumper name in braces {}.
J1 J2 J3 J11 J12 J31 J37 CS492x/CS493xx DSP clock {DSP Jumpers} Default: CLKIN CS492x/CS493xx WR pin {DSP Jumpers} Default: HI CS492x/CS493xx RD pin {DSP Jumpers} Default: LO Stake header for CS492x/CS493xx & CRD4923-MEM & CDB49300-MEM {DSP Jumpers} Stake header for CS492x/CS493xx {DSP Jumpers} RCA/Optical S/PDIF input selection {Audio Input Jumpers} Default: OPT Oscillator/External PLL select {System Clocking Jumpers} J44CS8404 Channel Status Bits {Audio Output Jumpers} Default: All bits HI (Not Populated). MASTER/SLAVE clocking mode of the CS5334 {Audio Input Jumpers} Default: SLAVE CS492x/CS493xx Analog Power {Power Jumpers} Default: INSTALLED CS492x/CS493xx Digital Power {Power Jumpers} Default: INSTALLED CS492x/CS493xx PSEL pin {DSP Jumpers} Default: HI PLD I/O Power Selection {Power Jumpers} Default: +3.3 V CS8414 SEL pin {Audio Input Jumpers} Default: HI (Not Populated). CS8414 CS12/FCK pin. {Audio Input Jumpers} Default: HI (Not Populated). PS1 pin of U26 {System Clocking Jumpers} Default: LO PS0 pin of U26 {System Clocking Jumpers} Default: HI DSP Power Selection {Power Jumpers} Default: +2.5 V AS1 pin of U26 {System Clocking Jumpers} Default: LO AS0 pin of U26 {System Clocking Jumpers} Default: LO PS2 pin of U26 {System Clocking Jumpers} Default: LO
J52 J59 J60 J62 J63 J65 J66 J67 J68 J69 J70 J71 J72
46
DS262DB2
CDB4923 CDB49300
16. APPENDIX J: SWITCH SUMMARY
Table 18 lists the jumper settings required for all four host interface modes of the CS492x/CS493xx. Table 19 shows all of the digital output formats that can be selected for the CS5334 with switch S4. Please see the CS5334 datasheet for a more detailed description of available digital output formats. Table 20 shows all of the digital input formats that can be selected for the CS4340 with S4. Please see the CS4340 datasheet for a more detailed description of available digital input formats. Table 21 shows all of the digital output formats that can be selected for the CS8414 with switch S1. Please see the CS8414 datasheet for a more detailed description of available audio serial port formats. Table 23 shows all of the digital input formats that can be selected for the CS8404A with switch S2. Please see the CS8404A datasheet for a more detailed description of available digital input format. Table 22. shows all available PLL settings for the external PLL on the CDB4923/4930. Table 24 lists all possible data routing possibilities and the associated MCLK source for the CDB4923/300.
RD J3 0 1 1 1
WR J2 1 0 1 1
PSEL J62 1 X 0 1
Host Interface Mode Serial I2C (PSEL == SCDIO) Serial SPI 8-bit Intel 8-bit Motorola
34DIF1 LO LO HI HI
34DIF0 LO HI LO HI
Digital Input Format 20-Bit Left Justified, Rising SCLK 20-Bit Left Justified, Falling SCLK 20 Bit I2S, Rising SCLK (default) Power Down
Table 19. CS5334 Digital Output Formats (S4)
Table 18. CS492x/CS493xx Host Interface Mode Selection
27DIF1 LO LO HI HI
27DIF0 LO HI LO HI
Digital Input Format 16-24 Bit I2S (default) 16-24 Bit Left Justified 24-Bit Right Justified 16-Bit Right Justified
M2 LO LO LO LO HI HI HI HI
M1 LO LO HI HI LO LO HI HI
M0 LO HI LO HI LO HI LO HI
Audio Serial Port Format Out, L/R, 16-24 Bits In, L/R, 16-24 Bits Out, L/R, I2S Compatible In, L/R, I2S (default) Out, WSYNC, 16-24 Bits Out, L/R, 16 Bits LSBJ Out, L/R, 18 Bits LSBJ Out, L/R, MSB Last
Table 20. CS4340 Digital Input Formats (S4)
Table 21. Digital Output Format settings for CS8414 (S1)
DS262DB2
47
CDB4923 CDB49300
PCLK Frequency 33.33 MHz 54 MHz 66.66 MHz 80 MHz 32 MHz 81 MHz 50 MHz 40 MHz
J72 LO LO LO LO HI HI HI HI
J67 LO LO HI HI LO LO HI HI
J68 LO HI LO HI LO HI LO HI
M2 LO LO LO LO HI HI HI HI
M1 LO LO HI HI LO LO HI HI
M0 LO HI LO HI LO HI LO HI
Audio Serial Port Format FSYNC & SCK Output Left/Right, 16-24 Bits Word Sync, 16-24 Bits Reserved Left/Right, I2S (default) LSB Justified, 16 Bits LSB Justified, 18 Bits MSB Last, 16-24 Bits
Table 22. PCLK Configurations
Table 23. Digital Input Format settings for CS8404A (S2)
PLD Mode 0 1 2 3 4 5 6 7
DATA SEL2 LO LO LO LO HI HI HI HI
DATA SEL1 LO LO HI HI LO LO HI HI
DATA SEL0 LO HI LO HI LO HI LO HI
CS492X/CS493XX CMPDAT S/PDIF -- CS8414 PC S/PDIF -- CS8414 S/PDIF -- CS8414 A/D -- CS5334
CS492X/CS493XX SDATAN1 A/D -- CS5334 A/D -- CS5334 S/PDIF -- CS8414 A/D -- CS5334 A/D -- CS5334 RESERVED RESERVED
MCLK MASTER J12 or DSP CS8414 DSP CS8414 CS8414 OSC/PLL
CONTROL SOURCE J11 & J12 J11 & J12 PC PC PC PC
Data and Control lines accessed via J11 and J12
Table 24. Data Selection Modes (Switch S3, PLD Version AB-X)
48
DS262DB2
* Notes *

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